In recent years, gate monolithcization has been under way to reduce costs by forming a gate driver on a liquid crystal panel with amorphous silicon. Such a gate monolithic is also referred to as gate driverless, panel-built-in gate driver, gate-in-panel, etc.
FIG. 21 shows a configuration of such a gate driver (scan drive circuit) as that described in Patent Literature 1.
The gate driver is configured to have a cascade arrangement of unit stages SRC11, SRC12, . . . , SRC1N, and SRC1D. Each of the unit stages receives a first clock CKV, in the case of an odd-numbered unit stage, or a second clock CKVB, in the case of an even-numbered unit stage, via its clock terminal CK. The first clock CKV and the second clock CKVB are opposite in phase to each other. The unit stages SRC11, SRC12, . . . , SRC1N, and SRC1D output gate terminal signals (G1, G2, . . . , GN, and GD) to a gate bus line via their respective output terminals OUT.
The first unit stage SRC11 receives a scan start signal STV via its first input terminal IN1, and the subsequent stages SRC12, SRC13, . . . , SRC1N, and SRC1D receive gate terminal signals from the previous unit stages via their respective first input terminals IN1. Further, the stages SRC11, SRC12, . . . , SRC1N, and SRC1D receive gate terminal signals from the next unit stages via their respective second input terminals IN2. Furthermore, each of the unit stages includes a first voltage terminal VOFF.